約 3,802,609 件
https://w.atwiki.jp/arcadegames/pages/176.html
== 概要 == HD6417095はセガのセガサターンやST-Vに使われているCPU,SH-2マイコン。HD6417604相当で、ピンアサインもほぼ同じ。 == 仕様 == HD6417095外観 出典：ウィキペディア HD6417095 (HITACHI) 144ピンQFP 28.7MHz駆動 == HD6417095 SH-2 ピンアサイン == 端子番号 端子名称 I/O 端子機能 1 D11 I/O Databus11 2 D12 I/O Databus12 3 D13 I/O Databus13 4 VCC - +5V 5 D14 I/O Databus14 6 VSS - 0V 7 D15 I/O Databus15 8 D16 I/O Databus16 9 D17 I/O Databus17 10 D18 I/O Databus18 11 D19 I/O Databus19 12 VCC - +5V 13 D20 I/O Databus20 14 VSS - 0V 15 D21 I/O Databus21 16 D22 I/O Databus22 17 D23 I/O Databus23 18 VCC - +5V 19 D24 I/O Databus24 20 VSS - 0V 21 D25 I/O Databus25 22 D26 I/O Databus26 23 D27 I/O Databus27 24 VCC - +5V 25 D28 I/O Databus28 26 VSS - 0V 27 D29 I/O Databus29 28 D30 I/O Databus30 29 D31 I/O Databus31 30 A0 I/O Addressbus0 31 A1 I/O Addressbus1 32 A2 I/O Addressbus2 33 VSS - 34 A3 I/O Addressbus3 35 A4 I/O Addressbus4 36 A5 I/O Addressbus5 37 A6 I/O Addressbus6 38 A7 I/O Addressbus7 39 A8 I/O Addressbus8 40 VCC - +5V 41 A9 I/O Adressbus9 42 VSS - 0V 43 A10 I/O Addressbus10 44 A11 I/O Addressbus11 45 A12 I/O Addressbus12 46 A13 I/O Addressbus13 47 A14 I/O Addressbus14 48 VCC - +5V 49 A15 I/O Addressbus15 50 VSS - 0V 51 A16 I/O Addressbus16 52 A17 I/O Addressbus17 53 A18 I/O Addressbus18 54 VCC - +5V 55 A19 I/O Addressbus19 56 VSS - 0V 57 A20 I/O Addressbus20 58 A21 I/O Addressbus21 59 A22 I/O Addressbus22 60 VCC - +5V 61 A23 I/O Addressbus23 62 VSS - 0V 63 A24 I/O Addressbus24 64 A25 I/O Addressbus25 65 A26 I/O Addressbus26 66 DACK0 O DMA0 acknowledge 67 VCC - +5V 68 DACK1 O DMA1 acknowledge 69 VSS - 0V 70 DREQ0 I DMA0 request 71 DREQ1 I DMA1 request 72 CS0# O Chip select 0 73 CS1# O Chip select 1 74 CS2# O Chip select 2 75 CS3# O Chip select 3 76 BS# I/O Bus cycle start 77 RD/WR# I/O Read/Write# 78 VSS - 0V 79 RAS#/CE# O RAS# for DRAM/SDRAM,CE# for Pseudo-SRAM 80 CAS#/OE# O CAS# for DRAM/SDRAM,OE# for Pseudo-SRAM 81 CASHH#/DQMUU/WE3# O Most significant byte selection signal for memory 82 CASHL#/DQMUL/WE2# O Second byte selection signal for memory 83 CASLH#/DQMLU/WE1# O Third byte selection signal for memory 84 VCC - +5V 85 CASLL#/DQMLL/WE0# O Least significant byte selection signal for memory 86 VSS - 0V 87 RD# O Read pulse 88 CKE O SDRAM clock enable control 89 WAIT# I Hardware wait request 90 NC(BEN?) 91 VSS - 0V 92 BACK#/BRLS# I Bus acknowledge in slave mode,bus request in master mode 93 BREQ#/BGR# O Bus request in slave mode,bus grant in master mode 94 WDTOVF# O Watchdog timer overflow signal output 95 FTOB O Free runnnig timer output B 96 VCC - +5V 97 FTOA O Free running timer output A 98 VSS - 0V 99 FTI I Free runninng time input 100 FTCI I Free running timer clock input 101 RXD I Serial port data in 102 TXD O Serial port data out 103 SCK I/O serial port clock in/out 104 VCC(PLL) - Power for on chip PLL +5V 105 MD0 I Mode select0 106 VSS(PLL) - 0V for on chip PLL 107 MD1 I Mode select1 108 CAP1 O External capacitance ppin for PLL 109 CAP2 O External capacitance ppin for PLL 110 MD2 I Mode select2 111 CKPACK# O Clock pause acknowledge output 112 CKPREQ#/CKM I Clock pause request input 113 VCC - +5V 114 EXTAL I Pin for connectiong crystal resonator 115 VSS - 0V 116 XTAL O Pin for connectiong crystal resonator 117 MD3 I Mode select3 118 CKIO I/O System clock input/output 119 MD4 I Mode select4 120 MD5 I Mode select5 121 VSS - 0V 122 RES# I Reset in 123 VCC - +5V 124 IVECF# O Interrupt vector fetch cycle 125 NMI I Non maskable interrupt request 126 IRL3# I External interrupt source request3 127 IRL2# I External interrupt source request2 128 IRL1# I External interrupt source request1 129 IRL0# I External interrupt source request0 130 D0 I/O Databus0 131 D1 I/O Databus1 132 VCC - +5V 133 D2 I/O Databus2 134 VSS - 0V 135 D3 I/O Databus3 136 D4 I/O Databus4 137 D5 I/O Databus5 138 D6 I/O Databus6 139 VCC - +5V 140 D7 I/O Databus7 141 VSS - 0V 142 D8 I/O Databus8 143 D9 I/O Databus9 144 D10 I/O Databus10 == リンク == 編集用 HD6417095ピンアサイン セガ(SEGA) ST-V == 外部リンク == セガサターン(基板バージョン VA0.5)の回路図(Rev.10) セガサターン(PAL仕様 基板バージョン VA0)サービスマニュアル セガサターン回路図 基板バージョンVA13相当(1) 下記と同じもの セガサターン回路図 基板バージョンVA13相当(2) 上記と同じもの
https://w.atwiki.jp/arcadegames/pages/113.html
== 基板一覧 == 全メーカーの基板（現在作成済みのページのみ） モデル メーカー SYSTEM II ナムコ SYSTEM16 セガ SYSTEM21 ナムコ SYSTEM24 セガ SYSTEM C セガ SYSTEM C2 セガ Cyclone カプコン CPS3 カプコン MJ-8956 ジャレコ MODEL1 セガ MODEL2 セガ MODEL3 セガ NAOMI セガ ST-V セガ TVG01 不明 X-BOARD セガ メガシステム(メガシステム16) ジャレコ メガシステム32 ジャレコ == リンク == == 外部リンク ==
https://w.atwiki.jp/arcadegames/pages/217.html
== 概要 == 315-6146はセガ NAOMI2に使用されているLSI。 == 仕様 == == 外観 == == リンク == セガ NAOMI
https://w.atwiki.jp/arcadegames/pages/92.html
== 概要 == 315-5423はMODEL1などに使われているLSI。 == 仕様 == MODEL1に実装されている315-5423 315-5423 HG62E130R37F (HITACHI) 168ピンQFP(HITACHI QFP5-168) 日立CMOSゲートアレイ HG62E SERIES GATE COUNT 13015 MAX.PAD COUNT 190 PACKAGE TYPE AND MAX.AVAILABLE SIGNAL PIN NUMBER QFP5-168 152 == リンク == セガ(SEGA) MODEL1 セガのLSI
https://w.atwiki.jp/arcadegames/pages/106.html
== 概要 == DL-2729はカプコンCPS3,Cycloneなどに使われているLSI。 参考 mamedev.org Viewing File src/mame/drivers/cps3.c http //mamedev.org/source/src/mame/drivers/cps3.c.html DL-2729 PPU SD10-505 (QFP304). Decapping reveals this is the main graphics chip. == 仕様 == CPS3やCycloneに実装されているDL-2729 DL-2729 PPU SD10-505 (TOSHIBA) 304ピンQFP == リンク == カプコン(CAPCOM) CPS3 カプコンのLSI
https://w.atwiki.jp/arcadegames/pages/80.html
== 概要 == V9938はMSXやNTTキャプテンシステム、ソニーの家庭用ビデオ編集機、ニチブツの基板などに搭載されているVDP。 == 仕様 == V9938 (ヤマハ) V9938 Ver.C1ピンマークがシボ無し平坦タイプ V9938 Ver.C1ピンマークがシボ有り半円状タイプ 画像出典：ウィキメディア コモンズ 画像出典：ココ 64ピンSDIP == リンク ==
https://w.atwiki.jp/arcadegames/pages/42.html
== 概要 == 315-5313はSYSTEM C,C2などに使われているVDP。メガドライブ,GENESISのVDP。 == 仕様 == SYSTEM C2の315-5313 メガドライブ(JP,HAA-2510,IC BD M5)の315-5313A 315-5313 (YAMAHA) 128ピンQFP == ピンアサインなど解析資料 == VDP pin assignments 315-5313 information (C) 2008 Charles MacDonald VDP pin assignments 315-5313 information (C) 2008 Charles MacDonald (BACKUP) ピン番号 ピン区分 ピン名称 機能 001 VRAM SD0 Serial data bus. 002 VRAM SD1 Serial data bus. 003 VRAM SD2 Serial data bus. 004 VRAM SD3 Serial data bus. 005 VRAM SD4 Serial data bus. 006 VRAM SD5 Serial data bus. 007 VRAM SD6 Serial data bus. 008 VRAM SD7 Serial data bus. 009 (N.C.) 010 VRAM SE_0 - SE_O? Serial data bus /OE 011 VRAM SC Serial clock. 012 VRAM RAS_1 Row address strobe. 013 VRAM CAS_1 Column address strobe. 014 (N.C.) 015 VRAM WE_0 - WE_1? Common write strobe. 016 VRAM OE_1 Common read strobe. 017 GND 0V 018 (N.C.) 019 (N.C.) 020 (N.C.) 021 (N.C.) 022 (N.C.) 023 (N.C.) 024 (N.C.) 025 (N.C.) 026 VIDEO SIGNAL AGC Video analog GND(0V). 027 VIDEO SIGNAL R-VIDEO Analog video Red out. 028 VIDEO SIGNAL G-VIDEO Analog video Green out. 029 VIDEO SIGNAL B-VIDEO Analog video Blue out. 030 VIDEO SIGNAL AVC Video analog power supply +5V. 031 VRAM AD0 Parallel address/data bus. 032 VRAM AD1 Parallel address/data bus. 033 VRAM AD2 Parallel address/data bus. 034 VRAM AD3 Parallel address/data bus. 035 VRAM AD4 Parallel address/data bus. 036 VRAM AD5 Parallel address/data bus. 037 VRAM AD6 Parallel address/data bus. 038 VRAM AD7 Parallel address/data bus. 039 VIDEO SIGNAL YS - Y1? 0=Transparent pixel, 1=Opaque pixel 040 VIDEO SIGNAL SPA/B 0= Sprite pixel.1= Non-sprite pixel. Y1 and SPA/B can be decoded as follows|Y1|A/B||0|0| Transparent pixel from any layer.|0|1| (This condition never occurs)|1|0| Opaque pixel from sprite layer.|1|1| Opaque pixel from background or backdrop layers. 041 VIDEO VSYNC 042 VIDEO C-SYNC 043 VIDEO HSYNC 044 VIDEO HL Horizontal counter latch enable.On a negative transition the horizontal counter is latched and can be read back by the CPU. It remains latched as long as HL is held low, otherwise it is free-running. 045 SEL0 0=VDP operates in Mark-III compatibility mode.1=VDP operates in normal mode. 046 PAL 0=VDP generates PAL compatible display timings.1=VDP generates NTSC compatible display timings. 047 RESET Reset input. 048 SEL1 Unknown.Tied to GND in Sega Genesis, Mega Play.Tied to +5V in System C2 and System 18. 049 CLK1 Outputs MCLK/7When MCLK=53.694175 MHz. = /CLK1=7.67 MHz (68K and YM2612 clock) 050 SBCR Outputs MCLK /15 (when PAL=H)Outputs MCLK/12 (when PAL=L)MCLK=53.694175 MHz. = SBCR=3.58 MHz (PAL=H, NTSC color subcarrier)SBCR=4.48 MHz (PAL=L, PAL color subcarrier) 051 CLK0 Outputs MCLK/15When MCLK=53.694175 MHz. = CLK0=3.58 MHz (Z80 clock). 052 MCLK Master clock input.In a typical system MCLK is 53.694175 MHz. 053 EDCLK Unknown.When MCLK=53.694175 MHz. = Unknown. 054 +5V 055 68000 D0 Data bus. 056 68000 D1 Data bus. 057 68000 D2 Data bus. 058 68000 D3 Data bus. 059 68000 D4 Data bus. 060 68000 D5 Data bus. 061 68000 D6 Data bus. 062 68000 D7 Data bus. 063 68000 D8 Data bus. 064 68000 D9 Data bus. 065 68000 D10 Data bus. 066 68000 D11 Data bus. 067 68000 D12 Data bus. 068 68000 D13 Data bus. 069 68000 D14 Data bus. 070 68000 D15 Data bus. 071 68000 A1 Address bus. 072 68000 A2 Address bus. 073 68000 A3 Address bus. 074 68000 A4 Address bus. 075 68000 A5 Address bus. 076 68000 A6 Address bus. 077 68000 A7 Address bus. 078 68000 A8 Address bus. 079 68000 A9 Address bus. 080 68000 A10 Address bus. 081 68000 A11 Address bus. 082 68000 A12 Address bus. 083 68000 A13 Address bus. 084 68000 A14 Address bus. 085 68000 A15 Address bus. 086 68000 A16 Address bus. 087 68000 A17 Address bus. 088 68000 A18 Address bus. 089 68000 A19 Address bus. 090 68000 A20 Address bus. 091 68000 A21 Address bus. 092 68000 A22 Address bus. 093 68000 A23 Address bus. 094 AVS Analog Sound Power supply Vcc(+5V). 095 PSG Sound output.PSG is the analog audio output from the SN76489-alike programmable sound generator in the VDP. AVS and AGS should be tied to +5V and GND respectively. 096 AGS Analog Sound GND(0V). 097 GND 0V 098 Z80 INT Interrupt request. 099 68000 BR Bus request. 100 68000 BGACK Bus grant acknowledge. 101 68000 BG Bus grant. 102 MRE0 Unknown.Tied to +5V in System C2.Controlled by the glue logic chip in the Genesis/MegaDrive. 103 INTAK Asserted to acknowledge a VDP-generated interrupt on IPL2-1.An external circuit would assert this when FC2-0 are high and AS is low. 104 68000 IPL1 Interrupt priority level, bit 1 105 68000 IPL2 Interrupt priority level, bit 2 106 Z80 IREQ I/O access. 107 Z80 ZRD Read strobe. 108 Z80 ZWR Write strobe. 109 Z80 M1 Opcode fetch strobe. 110 68000 AS Address strobe. 111 68000 UDS Upper data strobe. 112 68000 LDS Lower data strobe. 113 68000 R/W Read/write indicator. 114 68000 DTAK Data acknowledge. 115 UWR Asserted when UDS=L, R/W=L.Used as the upper byte lane strobe. 116 LWR Asserted when LDS=L, R/W=L.Used as the lower byte lane strobe. 117 OE0 Asserted when R/W=H within address range E00000-FFFFFF.During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it s restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.Typically used as work RAM OE with RAM mapped to E00000-FFFFFF.Refresh behaviorPeriodically RAS0 is delayed, and an extra OE0 pulse is added. 118 CAS0 Asserted when AS=L, R/W=H within address range 000000-DFFFFF.During DMA, it is asserted for 000000-FFFFFF. Hardware depending on it s restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.Because this signal overlaps the VDP area at $C00000-$DFFFFF,it is insufficient to use directly as a chip select despite being qualified by AS.If it was (for example) gated with A23, it could be used directly as ROM OE for fast ROM access when ROM CS is tied low.Typically used as a read strobe, and the address decoding logic restricts other devices from responding to it when an address is within the VDP range. 119 RAS0 Asserted when AS=L within address range E00000-FFFFFF.During DMA, it is asserted for 800000-FFFFFF. Hardware depending on it s restricted memory range during 68K control of the bus will need to disable devices that are mapped outside the range.Typically used as work RAM CS with RAM mapped to E00000-FFFFFF.Periodically the VDP will stretch a RAS0 cycle longer than normal, and insert an extra OE0 pulse. This may be to provide a refresh cycle for pseudo-static RAMs. 120 Color bus VD0 Pixel, bit 0 121 Color bus VD1 Pixel, bit 1 122 Color bus VD2 Pixel, bit 2 123 Color bus VD3 Pixel, bit 3 124 Color bus VD4 Palette, bit 0 125 Color bus VD5 Palette, bit 1 126 Color bus VD6 Shadow effect (0= not applied, 1= applied) 127 Color bus VD7 Hilight effect (0= not applied, 1= applied) VD7 and VD6 can be decoded as follows|VD7|VD6||0|0| Normal|0|1| Shadow|1|0| Hilight|1|1| (This condition never occurs) 128 +5V - Z80 interface - It is not clear how the VDP knows when to respond to the Z80 for accesses to $7F00-$7F1F, which map to $C00000-$C0001F. It could be that the glue logic chip forwards this request on the 68000 bus.When in Mark-III compatibility mode, the Z80 address and data bus are routed to the 68000 address and data bus. This way the VDP can check IREQ to determine when ports $40-$7F and $80-BF are being accessed, and respond to them accordingly. - Video sync signals - The function of VSYNC is defined by bit 6 of VDC register $0C 0= Pin outputs vertical sync. pulse.1= Pin outputs pixel clock.The function of HSYNC is defined by bit 5 of VDC register $8C 0= Pin outputs horizontal sync. pulse.1= Pin is fixed to H C-SYNC outputs a composite sync signal. It is TTL like VSYNC and HSYNC. - Video output - R-VIDEO,G-VIDEO,B-VIDEO are the analog RGB outputs. AGC and AVC should be tied to +5V and GND respectively. - Color bus - The color bus outputs information about the pixel data being displayed Y1 0= Transparent pixel, 1= Opaque pixel.SPA/B 0= Sprite pixel, 1= Non-sprite pixel.VD7 Hilight effect (0= not applied, 1= applied).VD6 Shadow effect (0= not applied, 1= applied).VD5 Palette, bit 1VD4 Palette, bit 0VD3 Pixel, bit 3VD2 Pixel, bit 2VD1 Pixel, bit 1VD0 Pixel, bit 0 - Unknown pins - Pins 9, 14, 18-25 seem to be no-connects and have no known function. Genesis 3 circuit schematic == リンク == セガ(SEGA) SYSTEM C ==外部リンク== MegaDrive Development Wiki 315-5313
https://w.atwiki.jp/arcadegames/pages/27.html
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https://w.atwiki.jp/arcadegames/pages/202.html
== 概要 == 315-5560はMODEL1などに使われているPCM音源LSI。 MODEL1 SOUND BOARD(SOUND BD)では、SOUND BOARDに１つ、OPTION BOARD(OPTION BD)に1つ実装されており、それぞれ楽曲パートと効果音パートに割り当てられている。 MODEL1 SOUND BOARD(SOUND BD)はMIDI入力で音楽、音声再生している。 == 仕様 == 315-5560 (YAMAHA) PCM 28ch 80ピンQFP == リンク == セガ(SEGA) MODEL1 == 外部リンク ==
https://w.atwiki.jp/arcadegames/pages/178.html
概要 CP SYSTEM(CPS1)はカプコンのシステム基板。メイン基板とROM基板、暗号復号化基板から構成される。 暗号復号化基板 92631C-6部品面 92631C-6半田面 NO DATA NO DATA 92641C-1部品面,生板状態 92641C-1半田面,生板状態