約 3,804,357 件
https://w.atwiki.jp/arcadegames/pages/27.html
砂場 このページは、Wikiの編集の練習のための「砂場」です。 ページ作成テストなどに利用してください。
https://w.atwiki.jp/arcadegames/pages/202.html
== 概要 == 315-5560はMODEL1などに使われているPCM音源LSI。 MODEL1 SOUND BOARD(SOUND BD)では、SOUND BOARDに１つ、OPTION BOARD(OPTION BD)に1つ実装されており、それぞれ楽曲パートと効果音パートに割り当てられている。 MODEL1 SOUND BOARD(SOUND BD)はMIDI入力で音楽、音声再生している。 == 仕様 == 315-5560 (YAMAHA) PCM 28ch 80ピンQFP == リンク == セガ(SEGA) MODEL1 == 外部リンク ==
https://w.atwiki.jp/arcadegames/pages/178.html
概要 CP SYSTEM(CPS1)はカプコンのシステム基板。メイン基板とROM基板、暗号復号化基板から構成される。 暗号復号化基板 92631C-6部品面 92631C-6半田面 NO DATA NO DATA 92641C-1部品面,生板状態 92641C-1半田面,生板状態
https://w.atwiki.jp/arcadegames/pages/146.html
== 概要 == 315-6201はセガ NAOMIに使用されている画像処理チップPowerVR2。 == 仕様 == == 外観 == imageプラグインエラー ご指定のURLはサポートしていません。png, jpg, gif などの画像URLを指定してください。 出典：ウィキメディアコモンズ Yaca2671 == リンク == セガ NAOMI
https://w.atwiki.jp/arcadegames/pages/63.html
== 概要 == 315-5360はSYSTEM16,SYSTEM18などに使われているLSI。メモリマッピングなどを行う。 315-5360 == 仕様 == Charles MacDonald's Home Pageより引用 Region allocation Like the System 16 hardware, the 315-5360 chip controls a user-definable memory map which consists of eight regions Region Alien Storm Clutch Hitter 0 Program ROM Program ROM (sockets ROM0-O,E) 1 Unused Program ROM (sockets ROM1-O,E) 2 VDP VDP 3 Work RAM Work RAM 4 Sprite RAM Sprite RAM 5 Tile/Text RAM Tile/Text RAM 6 Color RAM Color RAM 7 I/O area I/O area Alien Storm has only one set of program ROM sockets, while Clutch Hitter has two. Shadow Dancer is an exception; region 2 seems to be unused and region 1 is set to the VDP area at $C00000-$DFFFFF. It doesn t use the VDP for video, but obscures the tile banking routine by storing the bank value in word 0 of VRAM and reading it back later before copying the value to I/O port H. I don t have any information about the main or ROM board this game uses. For both Alien Storm and Clutch Hitter, region 2 must be mapped to $C00000-$DFFFFF in order to access the VDP. If not, writes do nothing and reads return the prefetch value. The VDP will still oprerate normally, but it s registers will be unavailable. The I/O area is a 16K space repeatedly mirrored throughout the banks allocated to it Region I/O chip offsets offsets Description $0000-$0FFF $00-$1F I/O chip registers and unused locations $1000-$1FFF $00-$1F I/O chip registers and unused locations $2000-$2FFF $20-$3F Video control register $3000-$3FFF $20-$3F /EXCS area The unusal mapping is due to the I/O chip having it s A5 input from 68K A12, and some additional logic uses /FMCS and 68K A11 to divide the /FMCS area into two parts, for the video control register and expansion /CS signal. Values written to odd bytes in the $2000-$3FFF range are stored in the video control register, explained later. Reads return the prefetch value and do not make the latch load in the contents of the data bus. Any expansion boards plugged into CN5 will appear at $3000-$3FFF. This is used by the D.D. Crew I/O board. The System 18 hardware uses the chip like so Port A - 1P controls D7 Joystick left (0= pressed, 1= released) D6 Joystick right (0= pressed, 1= released) D5 Joystick up (0= pressed, 1= released) D4 Joystick down (0= pressed, 1= released) D3 Button D (0= pressed, 1= released) D2 Button C (0= pressed, 1= released) D1 Button B (0= pressed, 1= released) D0 Button A (0= pressed, 1= released) Port B - 2P controls D7 Joystick left (0= pressed, 1= released) D6 Joystick right (0= pressed, 1= released) D5 Joystick up (0= pressed, 1= released) D4 Joystick down (0= pressed, 1= released) D3 Button D (0= pressed, 1= released) D2 Button C (0= pressed, 1= released) D1 Button B (0= pressed, 1= released) D0 Button A (0= pressed, 1= released) Port C - Bidirectional I/O port D7 To CN8 pin 3 D6 To CN8 pin 4 D5 To CN8 pin 5 D4 To CN8 pin 6 D3 To CN8 pin 8 D2 To CN8 pin 9 D1 To CN8 pin 10 D0 To CN8 pin 11 Port C is connected to a 74LS245 whose output goes to CN8. The CNT0 output pin controls the DIR input of the 74LS245. Port D - Miscellaneous output D7 ? D6 To color encoder /GRAY input (0= grayscale, 1= color) D5 To tilemap/sprite generator flip screen input (0= normal, 1= flip) D4 To pin 2 of CN8. D3 Coin lockout 2 D2 Coin lockout 1 D1 Coin meter 2 (increment counter on 0 to 1 transition) D0 Coin meter 1 (increment counter on 0 to 1 transition) Pin 2 of CN8 is a high current output capable of driving a lamp or coin meter. Bit 5 enables screen flipping for the tilemap and sprite layers, it is connected to both chips. It and bit 6 do not affect the VDP display which is separate. Port E - Service / Coin inputs D7 Always returns 1 D6 Select Game button (0= pressed, 1= released) D5 2P start button (0= pressed, 1= released) D4 1P start button (0= pressed, 1= released) D3 Service switch (0= pressed, 1= released) D2 Test switch (0= pressed, 1= released) D1 1P coin meter (0= Coin inserted, 1= No coin) D0 2P coin meter (0= Coin inserted, 1= No coin) Port F - DIP switch #1 D7 Switch 8 (1= Off, 0= On) D6 Switch 7 (1= Off, 0= On) D5 Switch 6 (1= Off, 0= On) D4 Switch 5 (1= Off, 0= On) D3 Switch 4 (1= Off, 0= On) D2 Switch 3 (1= Off, 0= On) D1 Switch 2 (1= Off, 0= On) D0 Switch 1 (1= Off, 0= On) Port G - DIP switch #2 D7 Switch 8 (1= Off, 0= On) D6 Switch 7 (1= Off, 0= On) D5 Switch 6 (1= Off, 0= On) D4 Switch 5 (1= Off, 0= On) D3 Switch 4 (1= Off, 0= On) D2 Switch 3 (1= Off, 0= On) D1 Switch 2 (1= Off, 0= On) D0 Switch 1 (1= Off, 0= On) Port H - Tile banking D7 Bit 3 of tile bank 2 D6 Bit 2 of tile bank 2 D5 Bit 1 of tile bank 2 D4 Bit 0 of tile bank 2 D3 Bit 3 of tile bank 1 D2 Bit 2 of tile bank 1 D1 Bit 1 of tile bank 1 D0 Bit 0 of tile bank 1 Output pins (summary) CNT0 - To 74LS245 DIR to control direction of port C connected to CN8. 0= Input from CN8 to port C 1= Output from port C to CN8 CNT1 - OR d with tilemap chip blank screen output, goes to /BLANK input of color encoder. 0= Screen blanked 1= Screen shown CNT2 - To enable input PAL controlling VDP display enable. 0= VDP output not shown 1= VDP output visible For Alien Storm, the lower three bits of each nibble select the tile ROM bank. If bit 3 of either nibble is set, the tile bank is always 0 and the tiles flicker a little. Most likely this is the high order address line which is unused in the ROM board. The bank select is from bit 12 of each word in tile RAM, and is always 0 for text layer tiles. Tile banking doesn t work at all on Clutch Hitter, though the banking hardware seems identical; the port H outputs are fed into an always-enabled 74LS157, whose output is the tile ROM high order address bits. The select input comes from the tilemap generator. I have the same problem with sprites which are not shown. The actual game itself runs fine, so there s some step I m leaving out, apparently. Another oddity is that CNT0 makes the screen flip, even though it is not connected to the flip screen signal and quite clearly goes to the DIR pin of the 74LS245 between port C and CN8. This holds true for both board types. Maybe an actual mistake in the hardware? == リンク == セガ(SEGA) SYSTEM16 SYSTEM18
https://w.atwiki.jp/arcadegames/pages/94.html
== 概要 == 315-5483はMODEL1などに搭載されているPLD。 == 仕様 == 315-5483 SIGNETICS PLD CK2605 20ピンDIP == リンク == セガ(SEGA) セガのLSI
https://w.atwiki.jp/arcadegames/pages/100.html
== 概要 == 315-5486はMODEL1などに搭載されているPLD。RGB信号系回路用？ == 仕様 == 315-5486 Lattice GAL16V8B25LP 20ピンDIP == リンク == セガ(SEGA) セガのLSI
https://w.atwiki.jp/arcadegames/pages/95.html
== 概要 == 315-5484はMODEL1などに搭載されているPLD(GAL)。 == 仕様 == 315-5484 Lattice GAL16V8B 20ピンDIP == リンク == セガ(SEGA) セガのLSI
https://w.atwiki.jp/arcadegames/pages/33.html
== 概要 == 315-5292はセガのSYSTEM24,MODEL1などに使われている画像用LSI。BG面のタイルマップ制御LSIとみられる。 == 仕様 == SYSTEM24に実装されていた315-5292 315-5292 (富士通) 160ピンQFP Sega System 24 hardware description Version 0.3(03/27/03) by Charles MacDonald 4.) Tilemap generator (315-5292)より引用。 4.) Tilemap generator (315-5292) The tilemap generator handles two 64x64 playfields, and it looks like there are two window planes that are probably used for static graphics like a status bar or menu. The tilemap generator is mapped to addresses $200000-2FFFFF $200000-20FFFF Name table data (64K) $280000-2FFFFF Pattern data (512K space, only 128K available) The Model 2 hardware uses the same chip with 512K of pattern data RAM. As the System 24 board only implements 128K, this means that some of the high order address bits are ignored. Due to mirroring they will appear to do nothing. The name table memory is divided into four 8K tables, which are composed of 64x64 entries, two bytes per entry. I believe the tables are arranged like so $200000-201FFF Playfield A $202000-203FFF Playfield A (Window?) $204000-205FFF Playfield B $206000-207FFF Playfield B (Window?) $208000-209FFF Playfield row/column scroll data (4K word sized values) $20A000-20BFFF First 16 words seem to be playfield scroll and control. $20C000-20DFFF Unknown (window control?) $20E000-20FFFF Unused The data at offsets $8000-$9FFF seems to be for row or column scrolling. The data at offsets $C000-$DFFF seems to be a name table sized bitmap which might be used for enabling the alternate window layer in tile sized units. The name table entries have the following format MSB LSB --nnnnnnnnnnnnnn Pattern name (Bits 13,12 have no effect, only 128K of RAM) -pppppppp------- Palette ?--------------- Unknown The patterns are 8x8 pixels, 4 bits per pixel. They are arranged as 4 bytes per line, 8 lines per pattern, for a total of 32 bytes per pattern. There is enough memory for 4096 patterns. If anyone designs a Model 2 emulator with debugging facilities, it might lead to more insight on how this chip works. (and vice-versa) Charles MacDonald's Home Page Old News (4/6)より引用。 Sega 315-5292 tilemap chip (System 24, Model 1) 656 pixels per scanline 69 pixels from /HSYNC high to /BLANK high (left border) 496 pixels from /BLANK high to /BLANK low (active display) 43 pixels from /BLANK low to /HSYNC low (right border) 48 pixels from /HSYNC low to /HSYNC high (horizontal sync. pulse) 424 scanlines per frame 25 scanlines from /VSYNC high to /BLANK high (top border) 384 scanlines from /BLANK high to /BLANK low (active display) 11 scanlines from /BLANK low to /VSYNC low (bottom border) 4 scanlines from /VSYNC low to /VSYNC high (vertical sync. pulse) Using 16 MHz pixel clock, 57.52 frames per second Setting $270001.b = $01 selects an invalid 512-scanline screen mode (same horizontal timings) where the display is enabled during the vertical sync. pulse and blanked at the wrong time. Maybe it s an unimplemented feature or used for chip testing, but it s definitely not useful. However it prevents frame buffer autoerase from working properly, so you can draw as many sprites as you want and keep the old ones. == ピンアサイン == SYSTEM24での接続例 端子番号 端子名 端子機能 その他 1 GND 0V 10 GND 0V 20 VCC +5V電源 30 GND 0V 41 GND 0V 50 GND 0V 60 VCC +5V電源 68 CLK1 16MHzクロック入力 69 CLK2 32MHzクロック入力 70 GND 0V 80 VCC +5V電源 81 GND 0V 90 GND 0V 110 GND 0V 121 GND 0V 130 GND 0V 138 VCC +5V電源 138 RESET# リセットパルス入力 140 VCC +5V電源 141 GND 0V 143 GND 0V 150 GND 0V 155 VCC +5V電源 160 VCC +5V電源 == リンク == セガ SYSTEM24 MODEL1 == 外部リンク == Sega System 24 hardware description Version 0.3(03/27/03) by Charles MacDonald 4.) Tilemap generator (315-5292) Charles MacDonald's Home Page Old News (4/6)
https://w.atwiki.jp/arcadegames/pages/145.html
== 概要 == 315-6119はセガ NAOMIに使用されている音源チップ。 == 仕様 == == 外観 == imageプラグインエラー ご指定のURLはサポートしていません。png, jpg, gif などの画像URLを指定してください。 出典：ウィキメディアコモンズ Yaca2671 == リンク == セガ NAOMI