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Overview The global 5G Chipset Industry share is set to cross USD 9.22 billion, with a 41.2% CAGR during the forecast period of 2020 to 2027. Market Research Future (MRFR) marks growing automation, use of IoT, expansion in data center network, hike in bandwidth, advanced antenna technology, participation from mobile operators, machine to machine communication, and others as the major traction providers. Segmentation The global 5G chipset market, as discussed by MRFR analysts, has been studied on the basis of a segmentation that includes the product, operational frequency, type, and verticals. By type, the market includes radio frequency integrated circuit (RFIC), cellular integrated circuit, application-specific integrated circuit (ASIC), and millimeter-wave integrated circuit. By operational frequency, the market comprises 26–39 GHz, below 6 GHz, and 39 and above GHz. By product, the market encompasses customer premise equipment and network infrastructure equipment. By vertical, the market discusses IT telecommunication, retail, government, automotive transportation, healthcare, industrial, energy utilities, and others. Request a Free Sample @ https //www.marketresearchfuture.com/sample_request/7148 Regional Analysis Structural benefit, investment scope, and the presence of major players are expected to put North America and Europe in advantageous positions. Asia Pacific would also gain from the booming electronics industry and growing incorporation of automation and IoT. Competitive Landscape The global market for 5G chipset is set to profit from the strategic moves of companies like Intel Corporation (US), Nokia Oyj (Finland), Qualcomm Inc (US), Xilinx Inc (US), IBM Corporation (US), Samsung Electronics Co Ltd (South Korea), Integrated Device Technology Inc (US), Qorvo Inc (US), Infineon Technologies AG (Germany), Broadcom Inc (US), Anokiwave (US), Analog Devices Inc (US), MACOM Technology Solutions Holdings Inc (US), Huawei Technologies Co., Ltd (China), Telefonaktiebolaget LM Ericsson Class B (Sweden), Cavium Inc (US), KT Corp (South Korea), ZTE Corporation (China), Hewlett Packard Enterprise Co (US), Fujitsu Ltd (Japan), and others. Industry News In September 2020, Samsung inked a deal with Qualcomm to produce the latter’s next-generation 5G mobile chipsets using the latest technology of the 5nm process. The deal has a valuation of around $844 million and will be the first time when Samsung will be producing chips for Qualcomm. The first one of this series will be Snapdragon 875. At present, Samsung produces 8nm devices for Qualcomm. But this deal ensures an advantageous position for Samsung from where it can take forward its TSMC technology. Samsung is also in talks with Intel to produce chips for the latter’s fabrication process. In September 2020, MediaTek declared that its 5G smartphone chip, the Dimensity 1000C, had hit the market in the United States. The Dimensity 1000C is expected to power LG’s newest device, the LG VELVET, on T-Mobile’s nationwide 5G network. It will deliver advanced AI capabilities, better display features, fast connectivity, and enhanced multimedia capabilities that would improve the user experience. The 7nm Dimensity 1000C is known for its super-fast 5G speeds and it helps in expanding the MediaTek’s 5G family of chipsets. The flagship series is also known to deliver full premium 5G experiences for smartphone users. During the CIVID-19 crisis, a lot of industries got hit by the impact of the pandemic, but the telecommunication industry stayed abreast and it found a way out by incorporating latest technologies and creating scope for further integration. It is slated to benefit more from the changing work cultures and business dynamics, which would inspire the expansion of the 5G chipset industry. Get Full Report @ https //www.marketresearchfuture.com/reports/5g-chipset-market-7148 Table of Contents 1 Executive Summary 2 Scope of The Report 2.1 Market Definition 2.2 Scope of The Study 2.2.1 Research Objectives 2.2.2 Assumptions Limitations 2.3 Market Structure Continued… Similar Report B2B Telecommunication Market Information by Solution (Unified Communication and Collaboration), Deployment (Fixed, Mobile), Organization Size (Large, Enterprise), Application (Industrial, Commercial) and regions Trending #MRFR Report** https //ictmrfr.blogspot.com/2022/04/geofencing-market-companies-growth-with.html https //blogfreely.net/pranali004/telecom-expense-management-market-size-impressive-cagr-changing-business-scope https //postheaven.net/pranali004/financial-app-industry-impressive-cagr-changing-business-needs-scope-of https //market-research-future.tribe.so/post/openstack-service-market-research-impressive-cagr-changing-scope-of-current--6263de46791566c10c79891e https //www.scutify.com/articles/2022-04-24-infrastructure-as-a-service-industry-cagr-changing-business-scope-of-current-and-future-industry- About Market Research Future At Market Research Future (MRFR), we enable our customers to unravel the complexity of various industries through our Cooked Research Report (CRR), Half-Cooked Research Reports (HCRR), Raw Research Reports (3R), Continuous-Feed Research (CFR), and Market Research Consulting Services. Contact Market Research Future (Part of Wantstats Research and Media Private Limited) 99 Hudson Street, 5Th Floor New York, NY 10013 United States of America 1 628 258 0071 (US) 44 2035 002 764 (UK) Email sales@marketresearchfuture.com Website https //www.marketresearchfuture.com
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このページはhttp //www.vgleaks.com/durango-cpu-overview/からの引用です 作業中・・・ Durango CPU Overview TheDurangoCPU brings a host of modern micro-architectural performance features to console development. With Durango, a familiar instruction set architecture and high performance silicon mean developers can focus effort on content and features, not micro-optimization. The trend towards more parallel power continues in this hardware; so, an effective strategy for multi-core computing is more important than ever. Architectural Overview The Durango CPU is structured as two modules. A module contains four x64 cores, each running a single thread at 1.6 GHz. Each core contains a 32 KB instruction cache (I-cache) and a 32 KB data cache (D-cache), and the 4 cores in each module share a 2 MB level 2 (L2) cache. In total, the modules have 8 hardware threads and 4 MB of L2. The architecture is little-endian. Four cores communicate with the module’s L2 via the L2 Interface (L2I), and with the other module and the rest of the system (including main RAM) via the Core Communication Interface (CCI) and the North Bridge. Caches The caches can be summarized as shown in the following table. Cache Policy Ways Set Size Line Size Sharing L1 I Read only 2 256 64 bytes Dedicated to 1 core L1 D Write-allocate, write-back 8 64 64 bytes Dedicated to 1 core L2 Write-allocate, write-back, inclusive 16 2048 64 bytes Shared by module The 4 MB of L2 cache is split into two parts, one in each module. On an L2 miss from one module, the hardware checks if the required line is resident in the other module—either in its L2 only, or any of its cores’ L1 caches. Checking and retrieving data from the other module’s caches is quicker than fetching it from main memory, but this is still much slower than fetching it from the local L1 or L2. This makes choice of core and module very important for processes that share data. Memory access result Cycles Notes L1 hit 3 Required line is in this core’s L1 L2 hit 17 Required line is in this module’s L2 Remote L2 hit, remote L1 miss 100 Required line is in the other module’s L2 Remote L2 hit, remote L1 hit 120 Required line is in the other module’s L2 in remote core’s L1 Local L2 miss, remote L2 miss 144-160 Required line is not resident in any cache; load from memory Both L1 and L2 caches have hardware prefetchers that automatically predict the next line required, based on the stream of load/store addresses generated so far. The prefetchers can derive negative and positive strides from multiple address sequences, and can make a considerable difference to performance. While the x64 instruction set has explicit cache control instructions, in many situations the prefetcher removes the need to manually insert these. The Durango CPU does not support line or way locking in either L1 or L2, and has no L3 cache. This document does not cover memory paging or translation lookaside buffers (TLBs) on the cores. Instruction Set Architecture The cores execute the x64 instruction set (also known as x86-64 or AMD64); this instruction set will be familiar to developers working on AMD or Intel based architectures, including that of desktop computers running Windows. x64 is a 64-bit extension to 32-bit x86 , which is a complex instruction set computer (CISC) with register-memory, variable instruction length, and a long history of binary backward compatibility; that is, some instruction encodings have not changed since the 16-bit Intel 8086. The x64 architecture requires SSE2 support, and Visual Studio makes exclusive use of SSE instructions for all floating-point operations. x64 deprecates older instruction sets x87, Intel MMX®, and AMD 3DNow!®. x64 supports the following instruction set extensions SIMD/vector instructions SSE up to SSE4.2 (including SSSE3 for packing and SSE4a), and AVX F16C half-precision float conversion BMI bit shifting and manipulation AES+CLMULQDQ cryptographic function support XSAVE extended processor state save MOVBE byte swapping/permutation VEX prefixing Permits use of 256-bit operands in support of AVX instructions LOCK prefix modifies selected integer instructions to be system-wide atomic The cores do not support XOP, AVX2, or FMA3/4 (fused multiply-add). Architecturally, the cores each have sixteen 64-bit general purpose registers, eight 80-bit floating point registers, and sixteen 256-bit vector/SIMD registers. The 80-bit floating point registers are part of x87 legacy support. Performance Durango CPU cores run at 1.6 GHz; this is half the clock rate of theXbox 360’s cores. Because of this, it is tempting to assume that the Xbox 360’s cores might outperform Durango’s cores. However, this is emphatically not true, for the reasons described in the following sections. Sub-ISA Parallelism and Micro-Operations Like most recent high-performance x64 processors, the cores do not execute the x64 instruction set natively; instead, internally instructions are decoded into micro-operations, which the processor executes. This translation provides opportunities to parallelize beyond traditional superscalar execution. Durango CPU cores have dual x64 instruction decoders, so they can decode two instructions per cycle. On average, an x86 instruction is converted to 1.7 micro-operations, and many common x64 instructions are converted to 1 micro-operation. In the right conditions, the processor can simultaneously issue six micro-operations a load, a store, two ALU, and two vector floating point. The core has corresponding pipelines two identical 64-bit ALU pipelines, two 128-bit vector float pipelines (one with float multiply, one with float add), one load pipeline, and one store pipeline. A core can retire 2 micro-operations a cycle. Out of Order Execution Xbox 360 CPU cores execute in-order (also calledprogram order)the instructions in exactly the order the compiler laid them out. The Xbox 360 CPU has no opportunity to anticipate and avoid stalls caused by dependencies in the incoming instruction stream, and no compiler can eliminate all possible pipeline issues. In contrast, the Durango CPU cores execute fully out of order (OOO), also calleddata order, since execution order is determined by data dependencies. This means the processor is able, while executing a sequence of instructions, to re-order the micro-operations (notthe x64 instructions) via an internal 64-entry re-order buffer (ROB). This improves performance by Starting loads and stores as early as possible to avoid stalls. Executing instructions in data-dependency order. Fetching instructions from branch destination as soon as the branch address is resolved. Register Renaming A low count of registers can cause execution of instructions to be unnecessarily serialized. Similar in concept to translating x64 instructions to micro-operations, register names used in the x64 instruction stream are not used as is, but are instead renamed to point at entries in a large internal physical register file (PRF)—Durango cores have a 64-entry, 64-bit, general-purpose PRF and a 72-entry, 128-bit, vector float PRF. With renaming, the processor can disentangle serialization by register name alone, and to get better throughput, it can push independent micro-operations to earlier positions in the execution order via OOO. Speculative Execution Instruction streams can be regarded as being divided into basic blocks of non-branching code by branches. CPUs with deep pipelines execute basic blocks efficiently, but they face performance challenges around conditional branches. The simplest approach—stall until the conditional is determined and the branch direction is known—results in poor performance. The Durango CPU is able to fetch ahead and predict through multiple conditional branches and hold multiple basic blocks in its re-order buffer, effectively executing ahead through the code from predicted branch outcomes. This is made possible via the core tracking which registers in the PRF represent speculative results—that is, those from basic blocks that are not currently certain to be executed. Once a branch direction is determined, if the core predicted the branch direction correctly, results from that basic block are marked as valid. If the core mispredicted, speculative results (which may include many basic blocks) are discarded, and fetching and execution then begins from the correct address. Store Forwarding With in-order execution, a store to memory followed shortly by a load from the same location can cause a stall while the contents of memory (usually via an L1 line) are updated; the stall ensures that the load gets the correct result, rather than a stale value. On Xbox 360, this commonly encountered penalty is called Load-Hit-Store. On Durango, the cores have store-forwarding hardware to deal with this situation. This hardware monitors the load store queue, looking for memory accesses with the same size and address; when it finds a match, it can short-cut the store and subsequent load via the physical register file, and thereby avoid significant pipeline stalls. Highly Utilized Out of Order Load Store Engine A Durango core is able to drive its load store unit at around 80-90% capacity,even on typical code, because the combination of OOO, register renaming, and store forwarding massively reduces pipeline flushes and stalls, permitting highly effective use of L1 bandwidth. This improvement is partly the result of the load store unit being able to reorder independent memory accesses to avoid data hazards loads can be arbitrarily re-ordered, and stores may bypass loads, but stores cannot bypass other stores. By contrast, the load store hardware in the Xbox 360 is utilized at about 15% capacity on typical code, due to the many pipeline bubbles from in-order execution on the cost-reduced PowerPC cores. In conjunction with pipeline issues, the major factors in the Xbox 360’s throughput being as low as 0.2 instructions per cycle (IPC) are L1 miss, L2 miss, and waiting for data from memory. Cache Performance The Durango CPU uses 64-byte cache lines, which makes a process less likely to waste bandwidth loading unneeded data. On Xbox 360, ensuring effective use of cache lines for 128-byte lines can be tricky. While a Durango core’s L1 data cache is the same size as on Xbox 360, it is not shared between two hyper threads, and it has better set associativity. L2 is effectively three times the size, for each hardware thread, and it has better associativity 512 KB per hardware thread on Durango versus approximately 170 KB per hardware thread on Xbox 360. L1 and L2 bandwidth will be more efficiently utilized on an automatic basis via prefetching, smaller cache lines, register renaming, OOO, and store forwarding. Advanced Branch Predictor Effective branch prediction increases the likelihood that speculative execution will execute the right code path. The Durango CPU cores have an advanced dynamic branch predictor, able to predict up to 2 branches per cycle. Rather than a branchdirection, an actual branchaddressis predicted, meaning the instruction fetch unit can speculatively fetch instructions without waiting for resolution of the branch instruction dependencies and the resultant target. The first-level sparse predictor stores information about the branch target for the first two branches in a cache line, hashed by line address in 4 KB of storage. The sparse information also indicates if more than 2 branches are present in that line, and indexes into a second-level dense predictor, by using a 4-KB set-associative cache of prediction information for branches in 8-byte chunks. A branch target address calculator checks relative branch predictions as early as possible in the pipeline to permit discarding incorrectly fetched instructions. In addition, the prediction unit contains a 16-entry call/return stack and a 32-entry out-of-page address predictor.
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Market Insight Globally, the Financial Cloud Market Growth is expected to have significant growth over the forecast period. The growth of the market can be attributed to the increasing digitalization across the globe and growing number of financial institutions that demand advanced IT solutions to gain genuine competitive advantage instead of only building and maintaining an expensive IT infrastructure. The financial cloud solutions enable enterprises to reach their existing as well as potential customers with right advertisement, in the right way, and at the right time, enabling enterprises to build a strong relationship with their customers. Due to these factors, the Financial Cloud Market Growth is expected to grow with significant rate in the upcoming years. However, high initial cost and lack of expertise, particularly among small and medium-sized enterprises (SMEs) in developing economies, are expected to hinder growth of the global Financial Cloud Market Growth. The study on the Financial Cloud Market Growth 2020 by Market Research Future has been conducted keeping the current proceeding within the financial cloud industry. COVID -19 Impact The report further considers the impact of the novel COVID-19 pandemic on the financial cloud market. It offers a clear review of the projected market fluctuations during the forecast period (2020-2027) at a pace of 22.7% CAGR while anticipating a valuation of USD 46.03 billion from USD 16.55 billion in the same period. Request a Free Sample @ https //www.marketresearchfuture.com/sample_request/7492 Operational efficiency is one more factor in driving the growth of the finance cloud market. A few years back, Roha Housing Finance wanted to issue loans within two hours instead of three days. After adopting cost-efficient cloud-based technology, it was able to offer end-to-end loan processing within seven days, which was 50% faster than the housing finance industry benchmark. Such instances probed the market for the financial cloud to rise at a substantial level and thus set the future to score toweringly with a host of opportunities. Further, MRFR finds that the financial industry is mostly prone to cyber threats due to the sensitivity of the data. It continues to develop in frequency, as the data generation volume grows. On this approach, Equifax incurred losses of about USD 1.35 billion from a devastating 2017 breach that affected more than half of the American customers as well as millions of the consumers in the United Kingdom. Here, the necessitate of adopting financial cloud came into action, which labelled to be highly successful. This instance also made the market of financial cloud more and more positive by the time, which resulted fruitful in the present time when the whole world is affected by COVID 19, and several industries went down. But the financial industry has less effect on it due to the firm base created for years. Segmental Analysis The global financial cloud market study has incorporated various segments that are component, cloud type, organization size, and sub-industry. Depending on the component segment, the market includes solutions and services. Among these, the solutions segment is further segmented into wealth management, customer management, security, financial forecasting and analytics, and others. The service segment has included professional and managed services. Depending on cloud type segment, the market has included public cloud and private cloud. Depending on organization size segment, the market has included large enterprises and small and medium-sized enterprises. Depending on the sub-industry segment, the market has included banking and financial services and insurance. Regional Framework The global market for global financial cloud is estimated to grow at a significant rate during the forecast period from 2018 to 2023. The geographical analysis of the market is studied for North America, Europe, Asia-Pacific, Middle East Africa, and South America. North America is presumed to have the largest market share in the global financial cloud market. The US, Canada, and Mexico are the leading countries in the region. The growth is attributed to the presence of large number of financial institutions and wealth management firms and a high degree of digitalization in the region. Asia-Pacific is anticipated to be the fastest growing region in the global financial cloud market over the forecast period. Rapidly increasing number of banking and insurance businesses and rising demand for advanced banking solutions in the region are the key driving factors for the growth of financial cloud market in the region. Key Players The prominent players in the financial cloud market are Google LLC (US), Microsoft Corporation (US), Oracle Corporation (US), IBM Corporation (US), Amazon Web Services, Inc. (US), SAP SE (Germany), Capgemini (France), Infosys (India), Fiserv, Inc. (US), FIS (US), and Temenos Headquarters SA (Switzerland). Browse Complete Report @ https //www.marketresearchfuture.com/reports/financial-cloud-market-7492 Table of Contents 1 Executive Summary 2 Scope of The Report 2.1 Market Definition 2.2 Scope of The Study 2.2.1 Research Objectives 2.2.2 Assumptions Limitations 2.3 Market Structure Continued… Similar Report B2B Telecommunication Market Information by Solution (Unified Communication and Collaboration), Deployment (Fixed, Mobile), Organization Size (Large, Enterprise), Application (Industrial, Commercial) and regions Trending #MRFR Report** https //ictmrfr.blogspot.com/2022/04/geofencing-market-companies-growth-with.html https //blogfreely.net/pranali004/telecom-expense-management-market-size-impressive-cagr-changing-business-scope https //postheaven.net/pranali004/financial-app-industry-impressive-cagr-changing-business-needs-scope-of https //market-research-future.tribe.so/post/openstack-service-market-research-impressive-cagr-changing-scope-of-current--6263de46791566c10c79891e https //www.scutify.com/articles/2022-04-24-infrastructure-as-a-service-industry-cagr-changing-business-scope-of-current-and-future-industry- About Market Research Future At Market Research Future (MRFR), we enable our customers to unravel the complexity of various industries through our Cooked Research Report (CRR), Half-Cooked Research Reports (HCRR), Raw Research Reports (3R), Continuous-Feed Research (CFR), and Market Research Consulting Services. Contact Market Research Future (Part of Wantstats Research and Media Private Limited) 99 Hudson Street, 5Th Floor New York, NY 10013 United States of America 1 628 258 0071 (US) 44 2035 002 764 (UK) Email sales@marketresearchfuture.com Website https //www.marketresearchfuture.com
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[98/12/16] 河野明敏 「大会】 35時間経過」 皆さんこんばんは。大会の途中経過です。 実況の方は後日お伝えします。 ● 勝率順(35時間経過) 前回 順位 ロボ名 試合数 総合 ASPHALT FOREST DESERT コンストラクター 1 →1 AKK/S 163 76.1% 83.3% 72.6% 64.0% 松井 和宏 2 →2 KAGEROU 156 68.3% 67.9% 61.7% 83.9% B.R.ドリトル(はた) 4 ▲3 TOULOUSE 146 58.6% 64.5% 50.0% 67.2% 冷罨法 3 ▽4 PENPEN02 124 57.3% 48.0% 54.8% 60.2% めかヨリタ 6 ▲5 MAHOMES 107 54.7% 53.4% 50.0% 56.3% 横浜 鯨一 5 ▽6 CATTAIL 156 53.2% 48.3% 53.8% 56.3% APFSDS(C.A.T.S.) 7 →7 .DOSA/J 102 50.0% 51.9% 52.4% 45.2% Sky Net Lab (歪王) 8 →8 MCGRAW 106 48.6% 52.9% 43.1% 47.2% mim 9 →9 HUTEN 96 46.9% 40.6% 50.0% 50.0% スナフ菌 10 →10 PENGUIN3 97 38.1% 29.7% 65.3% 13.8% M.ささき (B.I.R.D.) 11 →11 STARRUBY 90 37.8% 39.7% 40.6% 32.8% Ruy-Macmiran 12 →12 BURNER.2 117 36.3% 31.7% 34.3% 38.6% つう 13 →13 Z-001D 101 31.7% 25.0% 32.8% 37.8% Zhin 14 →14 MDM-0 100 31.5% 41.4% 8.9% 39.2% うおみず(IRI) 15 →15 MR-DATA 81 22.2% 23.3% 26.0% 17.3% o(^^)o E.Watanabe 今回は、35時間後の順位の変動を報告します。 - - - - - - - - - - - - - - - - - おまけ - - - - - - - - - - - - - - - - - ● Nifty大会用(BD率) 順位 ロボ名 BD率 得点 勝 敗 分 試合 勝率 wp1 wp2 コンストラクター 1 PENPEN02 100.0% 207 65 47 12 124 57.3% POW ENG めかヨリタ 2 CATTAIL 60.6% 180 57 47 52 156 53.2% POW SOL APFSDS(C.A.T.S.) 3 TOULOUSE 60.2% 170 48 23 75 146 58.6% CAN ATM 冷罨法 4 BURNER.2 57.9% 89 28 60 29 117 36.3% FLM ENG つう 5 Z-001D 53.7% 68 23 60 18 101 31.7% POW MIS Zhin 6 MR-DATA 45.5% 38 14 59 8 81 22.2% RFL FLM o(^^)o E.Watanabe 7 AKK/S 35.9% 258 103 18 42 163 76.1% CAN MIN 松井 和宏 8 HUTEN 35.8% 93 37 43 16 96 46.9% MIN ATM スナフ菌 9 STARRUBY 34.1% 63 24 46 20 90 37.8% LSR SOL Ruy-Macmiran 10 .DOSA/J 30.9% 89 34 34 34 102 50.0% RFL MIN Sky Net Lab (歪王) 11 MAHOMES 23.8% 86 33 23 51 107 54.7% MIN ATM 横浜 鯨一 12 PENGUIN3 22.8% 47 17 40 40 97 38.1% MIN SPK M.ささき (B.I.R.D.) 13 KAGEROU 22.2% 170 69 12 75 156 68.3% MIN MIS B.R.ドリトル(はた) 14 MCGRAW 16.9% 76 32 35 39 106 48.6% MIN SPK mim 15 MDM-0 13.3% 42 18 55 27 100 31.5% MIN ENG うおみず(IRI) ● Nifty大会用(P/B) 順位 ロボ名 P/B 得点 勝 敗 分 試合 勝率 wp1 wp2 コンストラクター 1 PENPEN02 1.67 207 65 47 12 124 57.3% POW ENG めかヨリタ 2 AKK/S 1.58 258 103 18 42 163 76.1% CAN MIN 松井 和宏 3 TOULOUSE 1.16 170 48 23 75 146 58.6% CAN ATM 冷罨法 4 CATTAIL 1.15 180 57 47 52 156 53.2% POW SOL APFSDS(C.A.T.S.) 5 KAGEROU 1.09 170 69 12 75 156 68.3% MIN MIS B.R.ドリトル(はた) 6 HUTEN 0.97 93 37 43 16 96 46.9% MIN ATM スナフ菌 7 .DOSA/J 0.87 89 34 34 34 102 50.0% RFL MIN Sky Net Lab (歪王) 8 MAHOMES 0.80 86 33 23 51 107 54.7% MIN ATM 横浜 鯨一 9 BURNER.2 0.76 89 28 60 29 117 36.3% FLM ENG つう 10 MCGRAW 0.72 76 32 35 39 106 48.6% MIN SPK mim 11 STARRUBY 0.70 63 24 46 20 90 37.8% LSR SOL Ruy-Macmiran 12 Z-001D 0.67 68 23 60 18 101 31.7% POW MIS Zhin 13 PENGUIN3 0.48 47 17 40 40 97 38.1% MIN SPK M.ささき (B.I.R.D.) 14 MR-DATA 0.47 38 14 59 8 81 22.2% RFL FLM o(^^)o E.Watanabe 15 MDM-0 0.42 42 18 55 27 100 31.5% MIN ENG うおみず(IRI) ● Nifty大会用(P/T) 順位 ロボ名 P/T 得点 勝 敗 分 試合 勝率 M/T コンストラクター 1 PENPEN02 7.667 207 65 47 12 124 57.3% 0 27 めかヨリタ 2 CATTAIL 2.022 180 57 47 52 156 53.2% 1 29 APFSDS(C.A.T.S.) 3 AKK/S 1.804 258 103 18 42 163 76.1% 2 23 松井 和宏 4 TOULOUSE 1.771 170 48 23 75 146 58.6% 1 36 冷罨法 5 KAGEROU 1.181 170 69 12 75 156 68.3% 2 24 B.R.ドリトル(はた) 6 Z-001D 0.861 68 23 60 18 101 31.7% 1 19 Zhin 7 BURNER.2 0.856 89 28 60 29 117 36.3% 1 44 つう 8 HUTEN 0.756 93 37 43 16 96 46.9% 2 03 スナフ菌 9 .DOSA/J 0.706 89 34 34 34 102 50.0% 2 06 Sky Net Lab (歪王) 10 MAHOMES 0.642 86 33 23 51 107 54.7% 2 14 横浜 鯨一 11 MCGRAW 0.517 76 32 35 39 106 48.6% 2 27 mim 12 STARRUBY 0.477 63 24 46 20 90 37.8% 2 12 Ruy-Macmiran 13 PENGUIN3 0.392 47 17 40 40 97 38.1% 2 00 M.ささき (B.I.R.D.) 14 MR-DATA 0.388 38 14 59 8 81 22.2% 1 38 o(^^)o E.Watanabe 15 MDM-0 0.269 42 18 55 27 100 31.5% 2 36 うおみず(IRI) では。 第2回 WWW (NIFTY通算第20回記念大会) 大会主催者 河野 明敏 (Akitoshi Kawano) NIFTY SERVE ID ********@nifty.ne.jp E-mail *****@*****.or.jp URL http //******.***.or.jp/*************/ www02 (8)「40時間経過」へ移動 《第2回 R.C.大会 in WWW》へ戻る